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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. AD5425 * 8-bit, high bandwidth multiplying dac with serial interface features 2.5 v to 5.5 v supply operation 50 mhz serial interface 8-bit (byte load) serial interface, 6 mhz update rate 10 mhz multiplying bandwidth 10 v reference input low glitch energy < 2 nv-s extended temperature range ?0 c to +125 c 10-lead msop package guaranteed monotonic 4-quadrant multiplication power on reset with brownout detection ldac function 0.4 a typical power consumption applications portable battery-powered applications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally-controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming functional block diagram general description the AD5425 is a cmos 8-bit current output digital-to-analog converter that operates from a 2.5 v to 5.5 v power supply, making it suited to battery-powered applications and many other applications. this dac utilizes a double buffered 3-wire serial interface that is compatible with spi , qspi, microwire, and most dsp interface standards. in addition, an ldac pin is provided, which allows simultaneous update in a multi-dac configuration. on power-up, the internal shift register and latches are filled with 0s and the dac outputs are at 0 v. as a result of processing on a cmos submicron process, this dac offers excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of 10 mhz. the applied external reference input voltage (v ref ) determines the full-scale output current. an integrated feedback resistor (r fb ) provides temperature tracking and full-scale voltage output when combined with an external i-to-v precision amplifier. the AD5425 dac is available in a small 10-lead msop package. sclk s ync AD5425 v ref i out 2 i out 1 r fb r 8-bit r-2r dac dac register sdin v dd gnd power-on reset l dac control logic and input shift register input latch * protected by u.s. patent no. 5,969,657; other patents pending.
rev. 0 e2e AD5425especifications 1 (v dd = 2.5 v to 5.5 v, v ref = 10 v, i out x = o v. all specifications t min to t max , unless other wise noted. dc performance measured with op177, ac performance with ad8038, unless otherwise noted.) parameter min typ max unit conditions static performance resolution 8 bits relative accuracy 0.25 lsb differential nonlinearity 0.5 lsb guaranteed monotonic gain error = = = ? = ? = a input capacitance 4 10 pf dynamic performance 2 reference multiplying bandwidth 10 mhz v ref = = ? = = = ? = = = = = ( ) = = ( ) = = = = =
rev. 0 AD5425 e3e parameter min typ max unit conditions power requirements power supply range 2.5 5.5 v i dd 0.4 5 al ogic inputs = 0 v or v dd 0.6 at a = 25 = +
rev. 0 e4e AD5425 timing characteristics 1, 2 parameter limit at t min , t max unit conditions/comments f sclk 50 mhz max max clock frequency t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 5 ns min data setup time t 6 3 ns min data hold time t 7 5 ns min sync rising edge to sclk falling edge t 8 30 ns min minimum sync high time t 9 0 ns min sclk falling edge to ldac falling edge t 10 12 ns min ldac pulse width t 11 10 ns min sclk falling edge to ldac rising edge notes 1 see figure 1. temperature range is as follows: y version: e40 + = = ( ) ( + ) ( = = = )
rev. 0 AD5425 e5e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD5425 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 (t a = 25 ) + + + + ( ) + + ja thermal impedance . . . . . . . . . . . 206 ( ) ( ) () () + + +
rev. 0 e6e AD5425 pin configuration i out 1 1 10 r fb sdin 56 sync sclk 47 ldac gnd 38 v dd i out 2 29 v ref AD5425 (not to scale) pin function descriptions pin no. mnemonic function 1i out 1 dac current output. 2i out 2 dac analog ground. this pin should normally be tied to the analog ground of the system. 3g nd digital ground pin. 4 sclk serial clock input. data is clocked into the input shift register on each falling edge of the serial clock input. this device can accommodate clock rates of up to 50 mhz. 5s di n serial data input. data is clocked into the 8-bit input register on each falling edge of the serial clock input. 6 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and the input shift register is enabled. data is transferred on each falling edge of the following 8 clocks. 7 ldac load dac input. updates the dac output. the dac is updated when this signal goes low or alternatively, if this line is held permanently low, an automatic update mode is selected whereby the dac is updated after 8 sclk falling edges with sync low. 8v dd positive power supply input. this part can be operated from a supply of 2.5 v to 5.5 v. 9v ref dac reference voltage input terminal. 10 r fb dac feedback resistor pin. establishes voltage output for the dac by connecting to external amplifier output.
rev. 0 t ypical performance characteristicseAD5425 e7e code inl (lsb) 0.20 0.10 0.15 0 ?0.05 0.05 ?0.10 ?0.15 ?0.20 050 100 150 250 200 t a = 25 c v ref = 10v v dd = 5v tpc 1. inl vs. code (8-bit dac) temperature ( c) error (mv) 5 4 ?3 ?4 0 ?2 3 2 ?5 ?60 ?40 ?20 0 20 40 60 80 100 120 140 ?1 1 v dd = 5v v dd = 2.5v v ref = 10v tpc 4. gain error vs. temperature ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 lsbs v bias (v) 1.0 0.5 1.5 2.0 2.5 max inl min inl max dnl min dnl v dd = 5v v ref = 0v tpc 7. linearity vs. v bias voltage applied to i out 2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?40 ?20 0 20 40 60 80 100 120 temperature ( c) i out leakage (na) i out 1 v dd 5v i out 1 v dd 3v 1.6 tpc 3. i out 1 leakage current vs. temperature ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 voltag e (mv) v bias (v) 0.5 1.0 1.5 gain error offset error t a = 25 c v dd = 3v v ref = 0v tpc 6. gain and offset errors vs. v bias voltage applied to i out 2 ?4.0 ?2.0 0 2.0 4.0 6.0 8.0 10.0 voltage (mv) 00.51.01 .5 2.0 2.5 v bias (v) gain error offset error t a = 25 c v dd = 5v v ref = 2.5v tpc 9. gain and offset errors vs. v bias voltage applied to i out 2 code dnl (lsb) 0.20 0.15 0.10 0.05 ?0.10 ?0.05 0 ?0.15 ?0.20 0 50 100 150 200 250 t a = 25 c v ref = 10v v dd = 5v tpc 2. dnl vs. code (8-bit dac) ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 lsbs 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 v bias (v) max inl min inl max dnl min dnl t a = 25 c v dd = 3v v ref = 0v tpc 5. linearity vs. v bias voltage applied to i out 2 ?0.5 0 0.5 1.0 1.5 2.0 2.5 voltag e (mv) v bias (v) 1.0 0.5 1.5 2.0 2.5 gain error offset error v dd = 5v v ref = 0v tpc 8. gain and offset errors vs. voltage applied to i out 2
rev. 0 e8e AD5425 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 lsbs v bias (v) 0.5 0 1.0 1.5 2.0 max inl bias min inl bias t a = 25 c v dd = 5v v ref = 2.5v max dnl bias min dnl bias tpc 10. linearity vs. v bias voltage applied to i out 2 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 11 0 100 1k 10k 100k 1m 100m frequency (hz) t a = 25 c v dd = 5v v ref = 3.5v c comp = 1.8pf ad5445 amplifier 10m gain (db) tpc 13. reference multiplying bandwidth?all 1s loaded ?9 ?6 ?3 0 3 10k 100k 1m 10m 100m frequency (hz) t a = 25 c v dd = 5v ad8038 amplifier v ref = 2v, ad8038 c c 1.47pf v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf gain (db) tpc 16. reference multiply- ing bandwidth vs. frequency and compensation capacitor voltage (v) 5.5 threshold voltage (v) 1.8 1.6 0 0.8 0.6 0.4 0.2 1.4 1.0 1.2 5.0 4.5 4.0 3.5 3.0 2.5 t a = 25 c v il v ih tpc 12. threshold voltages vs. supply voltage ?102 ?66 ?54 ?42 ?30 ?18 ?6 6 11 0 100 1k 10k 100k 1m 10m 100m frequency (hz) gain (db) t a = 25 c loading zs to fs 0 ?60 ?48 ?36 ?24 ?12 ?84 ?72 ?78 ?90 ?96 t a = 25 c v dd = 5v v ref = 3.5v input c comp = 1.8pf ad5445 amplifier all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off tpc 15. reference multiply- ing bandwidth vs. frequency and code ?120 ?100 ?80 ?60 0 20 11 0 100 1k 10k 100k 1m 10m frequency (hz) ?40 ?20 t a = 25 c v dd = 3v amp = ad8038 full scale zero scale power supply rejection tpc 18. power supply rejec- tion vs. frequency input voltage (v) current (ma) 0.7 0.6 0 0.5 0.4 0.3 5 4 3 2 1 0 0.2 0.1 v dd = 3v v dd = 2.5v v dd = 5v t a = 25 c tpc 11. supply current vs. input voltage time (ns) output voltage (v) 0.060 ?0.020 0.050 0.020 0.010 0.000 ?0.010 0.040 0.030 300 250 200 150 100 50 0 t a = 25 c v ref = 0v ad8038 amp c comp = 1.8pf ad5443 v dd 3v, 0v ref nrg = 0.088nvs 800h to 7ffh v dd 5v, 0v ref nrg = 0.119nvs, 800h to 7ffh v dd 3v, 0v ref nrg = 1.877nvs 7ffh to 800h v dd 5v, 0v ref nrg = 2.049nvs 7ffh to 800h tpc 14. midscale transition, v ref = 3.5 v ?90 ?85 ?80 ?65 ?60 11 0 100 1k 10k 100k 1m frequency (hz) ?75 ?70 t a = 25 c v dd = 3v v ref = 3.5v p-p thd + n (db) tpc 17. thd and noise vs. frequency
rev. 0 AD5425 e9e ?110 ?100 ?80 ?40 ?20 0 ?60 ?90 ?50 ?30 ?10 ?70 sfdr (db) 0 200k 400k 600k 800k 1m frequency (hz) t a = 25 c v dd = 5v v ref = 3.5v ad8038 amplifier c comp = 1.8pf 8k codes tpc 19. wideband sfdr, clock = 2 mhz, f out = 50 khz ?110 ?100 ?80 ?40 ?20 0 ?60 ?90 ?50 ?30 ?10 ?70 sfdr (db) 25k 30k 35k 40k 45k 50k 55k 60k 65k 70k 75 k frequency (hz) t a = 25 c v dd = 5v v ref = 3.5v ad8038 amplifier c comp = 1.8pf 8k codes tpc 22. narrowband sfdr, clock = 2 mhz, f out = 50 khz ?110 ?100 ?80 ?40 ?20 0 ?60 ?90 ?50 ?30 ?10 ?70 sfdr (db) 0 200k 400k 600k 800k 1m frequency (hz) t a = 25 c v dd = 5v v ref = 3.5v ad8038 amplifier c comp = 1.8pf 8k codes tpc 20. wideband sfdr, clock = 2 mhz, f out = 20 khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 imd (db) 10k 15k 20k 25k 30k 35 k frequency (hz) t a = 25 c v dd = 5v v ref = 3.5v ad8038 amplifier c comp = 1.8pf 8k codes tpc 23. narrowband imd ( 50%) clock = 2 mhz, f out 1 = 20 khz, f out 2 = 25 khz ?110 ?100 ?80 ?40 ?20 0 ?60 ?90 ?50 ?30 ?10 ?70 sfdr (db) 10k 12k 14k 16k 18k 20k 22k 24k 26k 28k 30 k frequency (hz) t a = 25 c v dd = 5v v ref = 3.5v ad8038 amplifier c comp = 1.8pf 8k codes tpc 21. narrowband sfdr, clock = 2 mhz, f out = 20 khz
rev. 0 e10e AD5425 terminology relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the end- points of the dac transfer function. it is measured after adjusting for zero and full scale and is normally expressed in lsbs or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of e1 lsb max over the operating temperature range ensures monotonicity. gain error gain error or full-scale error is a measure of the output error between an ideal dac and the actual device output. for these dacs, ideal maximum output is v ref e 1 lsb. gain error of the dacs is adjustable to 0 with external resistance. output leakage current output leakage current is current that flows in the dac ladder switches when these are turned off. for the i out 1 terminal, it can be measured by loading all 0s to the dac and measuring the i out 1 current. minimum current will flow in the i out 2 line when the dac is loaded with all 1s. output capacitance capacitance from i out 1 or i out 2 to agnd. output current settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. for these devices, it is specified with a 100 ? () () ( ) thd vvvv v = +++ ()
rev. 0 AD5425 e11e dac section the AD5425 is an 8-bit current output dac consisting of a standard inverting r-2r ladder configuration. a simplified diagram is shown in figure 2. the feedback resistor r fb has a value of r. the value of r is typically 10 k ? ( ? ? ) ( ) () () v?v out ref = d n 2 where d is the fractional representation of the digital word loaded to the dac, in this case 0 to 255, and n is the number of bits. note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. this dac is designed to operate with either negative or positive reference voltages. the v dd power pin is used by only the internal digital logic to drive the dac switches? on and off states. this dac is also designed to accommodate ac reference input signals in the range of e10 v to +10 v. v out = 0 to ?v ref sclk sdin gnd v ref sync i out 2 i out 1 r fb microcontroller agnd AD5425 notes 1. r1 and r2 used only if gain adjustment is required. 2. c1 phase compensation (1pf ? 2pf) may be required if a1 is a high speed amplifier. r1 r2 a1 v ref v dd v dd c1 figure 4. unipolar operation with a fixed 10 v reference, the circuit shown in figure 4 will give an unipolar 0 v to e10 v output voltage swing. when v in is an ac signal, the circuit performs 2-quadrant multiplication. table i shows the relationship between digital code and the expected output voltage for unipolar operation. table i. unipolar code table digital input analog output (v) 1111 1111 ev ref (255/256) 1000 0000 ev ref (128/256) = ev ref /2 0000 0001 ev ref (1/256) 0000 0000 ev ref (0/256) = 0
rev. 0 e12e AD5425 bipolar operation in some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. this can be easily accomplished by using another external amplifier and some external resistors as shown in figure 5. in this circuit, the second amplifier a2 provides a gain of 2. biasing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. the transfer function of this circuit shows that both negative and positive output voltages are created as the input data (d) is incremented from code zero (v out = ev ref ) to midscale (v out = 0 v ) to full scale (v out = + v ref ). vv v out ref ref = () ? d n /e 2 1 where d is the fractional representation of the digital word loaded to the dac and n is the resolution of the dac. when v in is an ac signal, the circuit performs 4-quadrant multiplication. table ii shows the relationship between digital code and the expected output voltage for bipolar operation. table ii. bipolar code table digital input analog output (v) 1111 1111 +v ref (127/128) 1000 0000 0 0000 0001 ev ref (127/128) 0000 0000 ev ref (128/128) stability in the i-to-v configuration, the i out of the dac and the inverting node of the op amp must be connected as close as possible, and proper pcb layout techniques must be employed. since every code change corresponds to a step function, gain peaking may occur if the op amp has limited gbp and there is excessive para- sitic capacitance at the inverting node. this parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in closed-loop applications. an optional compensation capacitor, c1 can be added in parallel with r fb for stability as shown in figures 6 and 7. too small a value of c1 can produce ringing at the output, while too large a value can adversely affect the settling time. c1 should be found empirically but 1 pfe2 pf is generally adequate for compensation. single-supply applications current mode operation figure 6 shows a typical circuit for operation with a single 2.5 v to 5 v supply. in the current mode circuit of figure 6, i out 2 and hence i out 1 is biased positive by an amount applied to v bias . in this configuration, the output voltage is given by vdr/rvvv out fb dac bias ? in bias = () () {} + vvtov v?v out bias out bias in == () = + ? = () ( )
rev. 0 AD5425 e13e voltage switching mode of operation figure 7 shows this dac operating in the voltage switching mode. the reference voltage, v in is applied to the i out 1 pin, i out 2 is connected to agnd and the output voltage is available at the v ref terminal. in this configuration, a positive reference voltage results in a positive output voltage making single-supply operation possible. the output from the dac is voltage at a constant impedance (the dac ladder resistance), thus an op amp is necessary to buffer the output voltage. the reference input no longer sees a constant input impedance, but one that varies with code. so, the voltage input should be driven from a low imped- ance source. v out v dd gnd v in i out 2 i out 1 r fb v dd v ref notes 1. additional pins omitted for clarity 2. c1 phase compensation (1pf? 2pf) may be required if a1 is a high speed amplifier. r2 r1 a1 figure 7. single-supply voltage switching mode operation it is important to note that v in is limited to low voltage because the switches in the dac ladder no longer have the same source- drain drive voltage. as a result, their on resistance differs, which degrades the linearity of the dac. also, v in must not go nega tive by more than 0.3 v or an inter- nal diode will turn on, exceeding the max ratings of the device. in this type of application, the full range of multiplying capabil- ity of the dac is lost. positive output voltage note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the resistor tolerance errors. to generate a negative reference, the reference can be level shifted by an op amp such that the v out and gnd pins of the reference become the virtual ground and e2.5 v respectively, as shown in figure 8. v out = 0 to +2.5v v dd = 5v gnd i out 2 i out 1 r fb v dd v ref c1 notes 1. additional pins omitted for clarity 2. c1 phase compensation (1pf? 2pf) may be required if a1 is a high speed amplifier. gnd v in v out adr03 +5v ?5v 1/2 ad8552 1/2 ad8552 ?2.5v a1 a2 figure 8. positive voltage output with minimum of components adding gain in applications where the output voltage is required to be greater than v in , gain can be added with an additional external amplifier or it can also be achieved in a single stage. it is important to take into consideration the effect of temperature coefficients of the thin film resistors of the dac. simply placing a resistor in series with the r fb resistor will causing mismatches in the temperature coefficients resulting in larger gain temperature coefficient errors. instead, the circuit of figure 9 is a recom- mended method of increasing the gain of the circuit. r1, r2, and r3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits where gains of greater than 1 are required. v out v dd gnd i out 2 i out 1 r fb v dd v ref c1 notes 1. additional pins omitted for clarity 2. c1 phase compensation (1pf? 2pf) may be required if a1 is a high speed amplifier. r 3 r 2 r2 v in r1 = r2r3 r2 + r3 gain = r2 + r3 r2 a1 figure 9. increasing gain of current output dac used as a divider or programmable gain element current steering dacs are very flexible and lend themselves to many different applications. if this type of dac is connected as the feedback element of an op amp and r fb is used as the input resistor as shown in figure 10, then the output voltage is inversely pro- portional to the digital input fraction d. for d = 1 e 2n the output voltage is v?v/d? v/ ? out in in ?n == () ()
rev. 0 e14e AD5425 cause the output voltage to be 16 v in . however, if the dac has a linearity specification of 0.5 lsb, then d can in fact have the weight anywhere in the range 15.5/256 to 16.5/256 so that the possible output voltage will be in the range 15.5 v in to 16.5 v in ?an error of +3% even though the dac itself has a maximum error of 0.2%. dac leakage current is also a potential error source in divider circuits. the leakage current must be counterbalanced by an oppo- site current supplied from the op amp through the dac. since only a fraction d of the current into the v ref terminal is routed to the i out 1 terminal, the output voltage has to change as follows: output error voltage due to dac leakage leakage r /d = () r is the dac resistance at the v ref terminal. for a dac leakage current of 10 na, r = 10 k ? ( ) ( ) ( ) () ( ) ( ) v p-p sc70, tsot, soic adr02 5 v 0.1% 3 ppm/ v p-p sc70, tsot, soic adr03 2.5 v 0.2% 3 ppm/ v p-p sc70, tsot, soic adr425 5 v 0.04% 3 ppm/ v p-p msop, soic table iv. some precision adi op amps suitable for use with AD5425 dacs part no. max supply voltage (v) v os (max) ( v) i b (max) (na) gbp (mhz) slew rate (v/ s) op97 + () () () () ( ) ( ) ()
rev. 0 AD5425 e15e microprocessor interfacing microprocessor interfacing to this dac is via a serial bus that uses standard protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. an ldac pin is also included. the AD5425 requires an 8-bit word with the default being data valid on the falling edge of sclk, but this is changeable via the control bits in the data-word. adsp-21xx to AD5425 interface the adsp-21xx family of dsps are easily interfaced to this family of dacs without extra glue logic. figure 11 shows an example of an spi interface between the dac and the adsp-2191. sck of the dsp drives the serial data line, din. sync is driven from one of the port lines, in this case spixsel. sclk sck AD5425 * sync spixsel sdin mosi adsp-2191 * * additional pins omitted for clarity figure 11. adsp-2191 spi to AD5425 interface a serial interface between the dac and dsp sport is shown in figure 12. in this interface example, sport0 is used to transfer data to the dac shift register. transmission is initiated by writing a word to the tx register after the sport has been enabled. in a write sequence, data is clocked out on each rising edge of the dsps serial clock and clocked into the dac input shift register on the falling edge of its sclk. the update of the dac output takes place on the rising edge of the sync signal. sclk sclk AD5425 * sync tfs sdin dt adsp-2101/ adsp-2103/ adsp-2191 * * additional pins omitted for clarity figure 12. adsp-2101/adsp-2103/adsp-2191 sport to AD5425 interface communication between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup and hold, data delay and data setup and hold, and sclk width. the dac interface expects a t 4 (sync falling edge to sclk falling edge setup time) of 13 ns minimum. consult the adsp-21xx user manual for information on clock and frame sync frequencies for the sport register. the sport control register should be set up as follows: tfsw = 1, alternate framing invtfs = 1, active low frame signal dtype = 00, right justify data isclk = 1, internal serial clock tfsr = 1, frame every word itfs = 1, internal framing signal slen = 0111, 8-bit data-word 80c51/80l51 to AD5425 interface a serial interface between the dac and the 8051 is shown in figure 13. txd of the 8051 drives sclk of the dac serial interface, while rxd drives the serial data line, d in . p3.3 is a bit-programmable pin on the serial port and is used to drive sync . when data is to be transmitted to the switch, p3.3 is taken low. the 80c51/80l51 transmits data in 8-bit bytes which is perfect for the AD5425 as it only requires an 8-bit word. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge. as a result, no glue logic is required between the dac and microcontroller interface. p3.3 is taken high following the completion of this cycle. the 8051 provides the lsb of its sbuf register as the first bit in the data stream. the dac input register requires its data with the msb as the first bit received. the transmit routine should take this into account. sclk txd 8051 * sync p1.1 sdin rxd AD5425 * * additional pins omitted for clarity figure 13. 80c51/80l51 to AD5425 interface mc68hc11 interface to AD5425 interface figure 14 shows an example of a serial interface between the dac and the mc68hc11 microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol) = 0, and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr)?see the 68hc11 user manual . sck of the 68hc11 drives the sclk of the dac interface, the mo si output drives the serial data line (d in ) of the ad5516. the sync signal is derived from a port line (pc7). when data is being transmitted to the ad5516, the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. pc7 is taken high at the end of the write. sclk sck AD5425 * sync pc7 sdin mosi mc68hc11 * * additional pins omitted for clarity figure 14. 68hc11/68l11 to AD5425 interface microwire to AD5425 interface figure 15 shows an interface between the dac and any mi crowire compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the dac input shift register on the rising edge of sk, which corresponds to the falling edge of the dac?s sclk.
rev. 0 e16e AD5425 sclk sk microwire * sync cs sdin so AD5425 * * additional pins omitted for clarity figure 15. microwire to AD5425 interface pic16c6x/7x to AD5425 the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit (ckp) = 0. this is done by writing to the synchronous serial port control register (sspcon). see the pic16/17 microcontroller user manual . in this example, i/o port ra1 is being used to provide a sync signal and enable the serial port of the dac. this microcontroller transfers eight bits of data during each serial transfer operation. figure 16 shows the connection diagram. sclk sck/rc3 pic16c6x/7x * sync ra1 sdin sdi/ rc4 AD5425 * * additional pins omitted for clarity figure 16. pic16c6x/7x to AD5425 interface pcb layout and power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the AD5425 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be estab- lished as close as possible to the device. these dacs should have ample supply bypassing of 10 () () 12 v, and +5 v supplies. the +12 v v dd and v ss are used to power the output amplifier, while the +5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 () ()
rev. 0 AD5425 e17e v dd v ss v out p1?13 p1?5 p1?4 p1?2 p1?3 p1?19 p1?20 p1?21 p1?22 p1?23 p1?24 p1?25 p1?26 p1?27 p1?28 p1?29 p1?30 sclk sdin sync ldac sclk sdin sync sdo/ ldac sclk sdin sync sdo/ ldac sdo gnd i out 2 v dd r fb v ref v ref v dd1 v ref v dd +v in v out trim gnd i out 1 AD5425/ad5426/ ad5432/ad5443 u1 u3 c5 4.7pf c1 0.1 f c2 10 f c7 10 f c8 0.1 f p2?3 p2?2 p2?1 p2?4 agnd v ss v dd1 v dd c11 0.1 f c12 10 f c3 10 f c4 0.1 f c5 0.1 f c13 0.1 f c14 10 f c15 0.1 f c16 10 f + + + u2 adr01ar 4 5 2 6 j2 j1 7 4 3 2 6 v? v+ + + c9 10 f c10 0.1 f + tp1 r1 = 0 ad8065ar 8 10 4 5 6 1 2 3 7 9 j3 j4 j5 j6 lk2 lk1 a b figure 17. schematic of the AD5425 evaluation board
rev. 0 e18e AD5425 eval?AD5425eb p1 p2 j2 j6 j5 j4 u1 u3 c11 u2 j3 vref vref j1 vout lk1 sdo/ldac sdo/ldac c10 c13 c14 c9 c1 r1 c2 c3 c6 c4 c16 c15 sync sync sdin sdin sclk sclk l dac lk2 sdo vdd vss vdd1 a gnd tp1 c8 figure 18. silkscreen?component side view (top layer) c7 c12 figure 19. silkscreen?component side view (bottom layer)
rev. 0 AD5425 e19e overview of ad54xx devices part no. resolution no. dacs inl t s max interface package features ad5403 * 82
rev. 0 d03161e0e1/04(0) e20e AD5425 back page_w/content outline dimensions 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba

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